The present invention relates to a new Design-For-Testability (DFT) technique aimed at detecting critical bridging faults, i.e. faults producing unacceptable extra delays in signal propagation, in CMOS and BiCMOS ICs. The invention overcomes the most important drawbacks of known DFT techniques based on built-in current sensors, by not requiring test devices in series with the functional blocks, thus minimizing the effects on circuit performance. Moreover it is capable of selectively detecting only faults that are really critical for the circuit operation, thus optimizing the margin for device rejection.
As is known, the testing of CMOS and BiCMOS ICs cannot be based on the assumption that all significant faults can be represented by means of the conventional stuck-at model. See J. A. Abraham and W. K. Fuchs, "Fault and Error Models for VLSI", 74 PROC. IEEE 639-654 (1986), which is hereby incorporated by reference.
In practice, a large portion of failures encountered in real circuits can be explained by the use of the so-called (resistive) bridging model 2 (herein considered to include also so-called stuck-on transistor faults), which implies the presence of a conductive path between power supply and ground. See H. Hao and E. McCluskey, "`Resistive Shorts` within CMOS Gates", in PROC. IEEE INTL. TEST CONF. 292-301 (1991), which is hereby incorporated by reference.
Such (resistive) bridging faults cause two main consequences:
1) the voltage at the output of a functional circuit (macro-gate or macro-cell) may assume "intermediate" values; PA1 2) a static current, commonly denoted IDDQ, flows from the power supply to ground.
As a result of the first effect, logic errors may or may not be produced according to whether or not the intermediate output voltages assumed by faulty (macro-)cells, lay on the same side of the logic threshold level of the fan-out gates, as in the correct situation. See M. Favalli, P. Olivo, M. Damiani and B. Ricco, "Fault Simulation of Unconventional Faults in CMOS ICs", 10 IEEE TRANSACTION ON CAD 677-682 (1991), which is hereby incorporated by reference.
Hereinafter, bridging faults (BFs) that may give rise to logic errors will be denoted LBFs, while others bridging faults that will not cause logic errors will be denoted as NLBFs.
In general, BFs must be detected, essentially because they inevitably degrade the circuit dynamic performance, while other effects, such as the extra power consumption associated with the IDDQ current, may be disregarded in many applications.
While LBFs can be detected essentially in the same way as stuck-at faults, NLBFs require special detection techniques. To this end, the second effect, mentioned above, may be exploited by sensing the presence of a "non-negligible" IDDQ. See Y. K. Malaiya and S. Y. H. Su, "A New Fault Model and Testing Technique for CMOS Devices", in PROC. IEEE INT. TEST CONF. 25-34 (1982); and L. Horning, J. Soden, R. Fritzmeier and C. Hawkins, "Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing", in PROC. IEEE INT. TEST CONF., 300-309 (1987); both of which are hereby incorporated by reference.
Indeed, this possibility is interesting, because a test for the presence of a static current could reveal the existence of both LBFs and NLBFs.
Moreover, IDDQ testing is potentially very effective and concise, because it merely requires fault activation (also for the detection of LBFs). In general, faults giving rise to measurable IDDQ can be detected with a set of test vectors much smaller than those of conventional ATPG algorithms. See P. Nigh and W. Maly, "Test Generation for Current Testing", in PROC. IEEE EUR. TEST CONF. 194-200 (1989), which is hereby incorporated by reference.
For these reasons IDDQ testing is attracting considerable interest, and, in conjunction with the trend toward increasing use of Design-For-Testability (DFT) techniques, significant efforts have been dedicated to the development of Built-In Current Sensors (BICSs) to be normally exploited as a complement tool of standard, stuck-at-model-oriented test methods, which are still largely implemented in an off-chip mode. See L. Horning, J. Soden, R. Fritzmeier and C. Hawkins, "Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing", in PROC. IEEE INT. TEST CONF. 300-309 (1987); D. Feltham, P. Nigh, R. Carley and W. Maly, "Current Sensing for Built-In Testing of CMOS circuits", in PROC. IEEE INT. CONF. COMPUTER DESIGN 454-457 (1988); and C. Hawkins, J. Soden, R. Fritzmeier and L. Horning, "Quiescent Power Supply Current Measurement for CMOS IC Defect Detection", 36 IEEE TRANS. INDUSTRIAL ELECTRONICS 211-218 (1989); all of which are hereby incorporated by reference.
A major drawback of all BICSs developed so far, is that they feature extra-devices (MOSFETs, BJTs, resistances, . . . ) in series with the functional circuit. The presence of such devices tends to degrade the dynamic performance of the functional circuit and it is necessary to realize these "extra-devices" with a considerably large area in order to minimize their negative effect. Above all, the use of series connected current sensors is incompatible with the trend toward scaled-down power supplies.
There is a need or utility for an improved DFT technique for testing for the existence of critical resistive bridging faults in CMOS and BiCMOS ICs that does not cause the above noted drawbacks of the known methods employing BICSs.
These objectives are satisfied by the DFT system of the present invention which is based on monitoring the presence of intermediate voltages at signal nodes of CMOS or BiCMOS logic ICs, rather than anomalously high static currents. Advantageously, the monitoring may be focused on a pre-established range of intermediate voltages, thus rendering the novel system of the invention intrinsically selective, namely able to reveal the presence of only BFs of actual concern for the correct operation of the circuit.